In the field of digital electronics, digital circuits operating at a first voltage level are often required to communicate within digital circuits operating at a different voltage level. For example, a first digital circuit within, say, a very large scale integrated (VLSI) circuit device, may be arranged to operate at a first voltage level. For example, such a first digital circuit may operate between a low power supply voltage of, say, 0V (e.g. a ground plane) and a high power supply voltage of, say, 2V. As such, this first digital circuit may operate at a 2V voltage level, with logic signals for this digital circuit existing at 0V for a low logical state and 2V for a high logical state. This first digital circuit may be required to communicate with (i.e. send and receive digital signals to and from) a second digital circuit. Such a second digital circuit may be external to the VLSI circuit device comprising the first digital circuit, and may be operating at a second voltage level. For example, such a second digital circuit may operate between a low power supply voltage of, say, 0V (e.g. a ground plane) and a high power supply voltage of, say, 3.3V. As such, this second digital circuit may operate at a 3.3V voltage level, with logic signals for this digital circuit existing at 0V for a low logical state and 3.3V for a high logical state. In order for two such digital circuits operating at different voltage levels to be able to communicate, a voltage conversion or translation is required for signals between the two digital circuits. Such voltage conversion/translation is typically performed by a voltage level shifter module circuit.
FIG. 1 illustrates a simplified circuit diagram of an example of a conventional voltage level shifter module circuit 100 arranged to convert a lower voltage digital signal received at an input thereof to an equivalent higher voltage digital signal output thereby. The voltage level shifter module circuit 100 comprises a first pair of input N-channel metal oxide semiconductor (NMOS) transistors N1 110 and N2 120. A gate 112 of the first input NMOS transistor N1 110 is operably coupled substantially directly to an input 105 of the voltage level shifter module circuit 100. A gate 122 of the second input NMOS transistor N2 120 is operably coupled to the input 105 of the voltage level shifter module circuit 100 via an inverter 115. Sources 114, 124 of the first and second input NMOS transistors N1 110, N2 120 are operably coupled to a low voltage power supply VSSIO 125.
The voltage level shifter module circuit 100 further comprises a pair of cross-coupled P-channel metal oxide semiconductor (PMOS) transistors P1 130, P2 140. Sources 134, 144 of the cross-coupled PMOS transistors P1 130, P2 140 are operably coupled to a high voltage power supply VDDIO 135. Drains 136, 146 of the cross-coupled PMOS transistors P1 130, P2 140 are operably coupled to differential output nodes 150, 155 respectively of the voltage level shifter module circuit 100. A gate 132 of the first cross-coupled PMOS transistor 130 is operably coupled to a first of the differential output nodes 155, to which the drain of the second cross-coupled PMOS transistor is also operably coupled. A gate 142 of the second cross-coupled PMOS transistor 140 is operably coupled to a second of the differential output nodes 150, to which the drain of the first cross-coupled PMOS transistor is also operably coupled.
The voltage level shifter module circuit 100 illustrated in FIG. 1 further comprises a pair of cascode NMOS transistors N3 160, N4 170 and a pair of cascode PMOS transistors P3 180, P4 190. The cascode transistor pairs are operably coupled between the input NMOS transistors N1 110, N2 120 and the cross-coupled PMOS transistors P1 130, P2 140, and ensure the voltages across the terminals of the various transistors within the voltage level shifter module circuit 100 remain within the technology limits for the thickness of the transistor gate oxides, as is well known in the art. Thus, the voltage level shifter module 100 consists of two branches of transistors that are differentially switched. The first branch of transistors comprises the NMOS transistors N1 110 and N3 160 and the PMOS transistors P3 180 and P1 130. The second branch of transistors comprises the NMOS transistors N2 120 and N4 170 and the PMOS transistors P4 190 and P2 140.
In an ideal scenario, the power supplies VSSIO 125 and VDDIO 135 are arranged to comprise voltages of, say, 0V and 3.3V respectively, whilst the input signal 105 is generated by a digital circuit operating at a 2V voltage level, with logic signals for the input signal 105 comprising 0V for a low logical state and 2V for a high logical state. The gates 162, 172 of the cascode NMOS transistors N3 160, N4 170 are operably coupled to a reference voltage signal VREF_1 165, whilst the gates 182, 192 of the cascode PMOS transistors P3 180, P4 190 are operably coupled to a reference voltage signal VREF_2 185. The reference voltage signals VREF_2 185 and VREF_1 165 comprise voltage levels between the power supplies VSSIO 125 and VDDIO 135, such equal to VDDIO/2. Accordingly, in this ideal scenario the reference voltage signals VREF_2 185 and VREF_1 165 comprise voltages of 1.65V.
The voltage level shifter module circuit 100 operates as follows. Assuming the input 105 comprises a high logical level of 2V, the input NMOS transistor N1 110 is driven into a conductive state by the high input signal 105, which pulls the source 164 of the cascode NMOS transistor N3 160 down to VSSIO 125. At the same time, the input NMOS transistor N2 120 is driven into a non-conductive state by the low inverted input signal output by the inverter 115. This results in the source 174 of the cascode NMOS transistor N4 170 charging up to VREF_1 165. Since the gate voltages of the cascode NMOS transistors N3 160, N4 170 are held at VREF_1 165, the cascode NMOS transistors N3 160, N4 170 are driven into conductive and non-conductive states respectively. As a result, the drain 186 of the cascode PMOS transistor P3 180 is pulled down to VSSIO 125, whilst the drain 196 of the cascode PMOS transistor P4 190 is charged up to VDDIO 135. Since the gate voltages of the cascode PMOS transistors P3 180, P4 190 are held at VREF_2 185, voltages at the sources 184, 194 of the cascode PMOS transistors P3 180, P4 190 will not drop below VREF_2 185. The cross-coupled PMOS transistors P1 130, P2 140 operate in a similar manner to a current sense circuit. As such, the output node 150 to which the source 184 of cascode PMOS transistor P3 180, the drain 136 of the cross-coupled PMOS transistors P1 130 and the gate 142 of the cross-coupled PMOS transistor P2 140 are operably coupled is discharged until it reaches: VREF_2+|VPth|, VPth being the threshold voltage for the PMOS transistors. This discharging of the output node 150 drives the cross-coupled PMOS transistor P2 140 into a conductive state, which charges the output node 155 to which the source 194 of cascode PMOS transistor P4 190, the drain 146 of the cross-coupled PMOS transistors P2 140 and the gate 132 of the cross-coupled PMOS transistor P1 130 are operably coupled to VDDIO 135. This charging of the output node 155 to VDDIO 135 drives the cross-coupled PMOS transistor P1 130 into a non-conductive state. The reverse of the above described operation of the voltage level shifter module circuit 100 occurs when the input 105 comprises a low logical level of 0V.
With a typical +/−10% tolerance margin a minimum permissible voltage for VDDIO 135 is 3.0V. However, the performance (timing delays, rise/fall delay difference) of such a conventional voltage level shifter module circuit 100 degrades drastically when VDDIO 135 drops to 3.0V. The reason for such performance degradation is as follows. When VDDIO=3.0V, VREF_2=VDDIO/2=1.5v. When the input 105 transitions from, say, 0V to 2V, the output node 150 is discharged until it reaches: VREF_2+|VPth|, VPth being the threshold voltage for the PMOS transistors and typically equal to around 0.75V. Thus, when VDDIO 135 is 3.0V, the output node 150 discharges to 1.5V+0.75V=2.25V. This 2.25V is applied to the gate 142 of the PMOS transistor P2 140. Since the source 144 of the PMOS transistor P2 140 is tied to VDDIO 135, VGS for the PMOS transistor P2 140=3.0V−2.25V=0.75V. Thus, as can be seen, when VDDIO 135 is 3.0V the voltage applied to the gate 142 of the PMOS transistor P2 140 when the input 105 transitions from 0V to 2V is only sufficient to drive the PMOS transistor P2 140 into its sub-threshold region of operation, with very low drive capability.
Such poor performance when VDDIO 135 is at or near its minimum permissible voltage of 3.0V prevents high speed operation of the voltage level shifter module circuit 100 under such permitted operating conditions.